Field effect transistor driver using capacitor feedback

ABSTRACT

THIS INVENTION RELATES TO A DRIVER FOR MOST DEVICES COMPRISING A CAPACITOR, INCLUDING MEANS FOR CHARGING AND PREVENTING DISCHARGE OF THE CAPACITOR, CONNECTED BETWEEN THE GATE ELECTRODE OF THE OUTPUT TRANSISTOR AND THE OUTPUT FOR FEEDING BACK THE OUTPUT VOLTAGE TO THE GATE ELECTRODE, WHEREBY RELATIVELY HIGHER VOLTAGE AND CURRENT OUTPUT FROM THE DRIVER IS ACHIEVED WITHOUT INCREASING THE SUPPLY VOLTAGE.

R. w. POLKINGHORN arm. Re. 27,

March 14, 1972 FIELD EFFECT TRANSISTOR DRIVER USING CAPACITOR FEEDBACK Origina1 Filed Dec.

2 Sheets-Sheet 1 T m m FIG.

{ie E:

INVENTORS ROBERT W. POLKINGHORN ARTHUR F. ,PFEIFER BY WILLIAM H. DIERKING ATTORNEY FIELD EFFECT TRANSISTOR DRIVER USING CAPACITOR FEEDBACK Original Filed Dec.

March 2 R. w. POLKINGHORN E'r L 2 Sheets-Sheet 2 INPUT TRUE,

OUTPUT lNvEN'mRs ROBERT w. POLKINGHORN ARTHUR F. PFEIFER BY WILLMMH; DIERKING ATTORNE? GATE (c) United States Patent Oflice Re. 27,305 Reissued Mar. 14, 1972 27,305 FIELD EFFECT TRANSISTOR DRIVER USING CAPACITOR FEEDBACK Robert W. Polkinghorn, Huntington Beach, Arthur F. Pfeifer, Whittier, and William H. Dierking, Orange, Calif., assignors to North American Rockwell Corporation Original No. 3,506,851, dated Apr. 14, 1970, Ser. No. 601,774, Dec. 14, 1966. Application for reissue May 25, 1970, Ser. No. 40,142

Int. Cl. H03]: 17/00 U.S. Cl. 307-251 5 Claims Matter enclosed in heavy brackets I: appears in the original patent but forms no part of this reissue specification; matter printed in italics indicates the additions made by reissue.

ABSTRACT OF THE DISCLOSURE This invention relates to a driver for MOS devices comprising a capacitor, including means for charging and preventing discharge of the capacitor, connected between the gate electrode of the output transitor and the output for feeding back the output voltage to the gate electrode, whereby relatively higher voltage and current output from the driver is achieved without increasing the supply voltage.

BACKGROUND OF THE INVENTION Field of the invention The invention pertains to a metal oxide semiconductor (MOS) transistor driver for use with other MOS devices such as gating devices.

Description of the prior art Present art MOS gating devices ordinarily may not provide enough current to drive succeeding stages. It is necessary to insert a driver between the gating device and the succeeding stages to increase the voltage and current available to the succeeding stages. However, and inasmuch as, the driver devices produced with existing techniques occupy a portion of the substrate structure adjacent to the gating devices, the driver should be as small in size as possible and "should have as low a power dissipation as possible so as not to impair the operation of the other devices.

Many driver dissipate excessive power and are not as efficient as desired because of the threshold voltage drop between the supply voltage and the output of an MOS transistor. In other words, the output voltage from a driver is ordinarily less negative than the supply voltage by one threshold voltage value for each stage of the driver. Since most drivers use at least two stages, the output from the last stage may be two thresholds lower than the supply voltage. Therefore, for a given or required output voltage, the supply voltage must be increased to compensate for the voltage drop. The increased voltage causes an increase in power dissipation from the driver. One example of a threshold voltage drop is five volts. An increase of the supply voltage may also necessitate a re-design of other circuits unless two supply voltages are used.

SUMMARY OF THE INVENTION Briefly, the present invention provides a driver for use with MOS gating devices in which the output voltage from the driver is fed back, or supplied, to the gate electrode of the output transistor by means of a capacitor coupled between the gate electrode and the output electrode. The capacitor is initially charged during a first interval of time to the level of the output voltage of a first stage as a function of the state of an input signal to the driver. Under conditions where the input signal is true, the capacitor is charged through a relatively low resistance path. When the input becomes false, the capacitor retains its charge because a relatively high resistance path replaces the relatively low resistance. The gate voltage of the output transistor increases through the capacitor but the voltage differential between the gate and the output electrode remains fixed. The feedback voltage holds the output transistor on and sets the output to the value of the supply voltage.

In certain applications, where more current is required, an additional driver stage may be added. In such cases, the output voltage may be one threshold lower than the supply voltage.

In other embodiments, an additional capacitor or a RC network may be added to delay the change in output voltage while the feedback capacitor is being charged.

The capacitor which serves as a feedback capacitor can be formed at the same time as the MOS devices are formed. In other words, when the gate electrode for the device is formed, the metal portion forming the gate is increased in dimensions to serve as one side of a capacitive plate. A portion of the source electrode of the MOS transistor is similarly increased in dimension to comprise the other plate of the capacitor. As a result, the one capacitive plate is integrally formed with the gate electrode and the other plate is integrally formed with the source electrode.

Therefore, it is an object of this invention to provide an M05 driver having a relatively increased voltage and current producing capability.

It is a further object of this invention to provide an improved MOS driver using capacitive feedback.

It is another object of this invention to provide an MOS transistor usable with an MOS driver using capacitive feedback wherein the capacitive element is produced at the same time as the MOS transistor comprising part of the driver is produced.

These and other objects of this invention will become more apparent in connection with the following drawings of which,

BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 shows a preferred embodiment of the MOS driver using a capacitive feedback.

FIGURE 2 shows a preferred embodiment of the FIGURE 1 device using a push-pull output stage.

FIGURE 3 shows a second embodiment of the MOS driver using a push-pull output stage.

FIGURE 4 shows a third embodiment of the MOS driver using a push-pull output stage.

FIGURE 5 shows a layout of the FIGURE 1 embodiment on a substrate, including a representation of capacitor C.

FIGURE 6 shows a representation of waveforms for the FIGURE 1 embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIGURE 1, wherein is illustrated MOS driver 1, comprising capacitor C, connected between output 3 and gate electrode 4 of MOS transistor 5. Capacitor C is also connected to source electrode 6 of MOS transistor 7. Gate electrode 8 and drain electrode 9 )f transistor 7 are connected to supply voltage V. Source electrode 10 of transistor 5 is connected to output 5 and drain electrode 11 of transistor 12. Input logic 2 s comprised of transistor 12. The gate electrode 13 of ransistor 12 is designated as the input. Source electrode [4 is connected to a ground level. Drain electrode 15 of ransistor 5 is connected to supply voltage V.

Input transistor 12 is made relatively larger in size with respect to transistors 5 and 7 so that the output will tpproximate the ground level appearing on the source elec- ;rode when the input transistor is turned on by a negative :ignal applied to its gate electrode.

Although a single transistor is shown for the input logic, t should be obvious that several devices in various conigurations, may be used as the input logic. Also, source :lectrode 14 need not be connected to ground but could be :onnected to a single source. A single device is shown for iimplifying the description of the preferred embodiment. it should also be noted that the device can be produced 11 an embodiment which does not use input logic but )nly requires the use of a transistor or similar switching levice for controlling the voltage appearing at the output.

In operation, as shown by the curves in FIGURE 6, vhen the input transistor is turned on, the output is aparoximately ground, or zero, volts (curves a and b). Fransistor 7 is held on because its gate is connected to V and therefore, is at least one threshold more negative han its source electrode.

During the interval of time that transistor 12 is on, :apacitor C is charged to the voltage level of the supply, V, plus the threshold voltage, V of transistor 7. In :tfect, the capacitor is charged to the difference between he voltage at the output and the voltage at the gate. iince the output voltage is approximately zero, the capacior is charged to the level indicated above. The voltage evel of the capacitor and the gate electrode of transistor 5, vhile the capacitor is being charged, is shown in curve c. When the capacitor is fully charged transistor 7 is turned )if to place a high resistive path between the capacitor 1nd the supply. Although the resistance is relatively high, ome leakage does occur. The leakage through the high esistance accounts for the peaks shown in curve c.

When the input goes false, or zero, for the logical order tdopted the output goes negative. The output voltage is 'ed back to the gate electrode (curve As a result, the gate becomes more negative than the output by at least wo thresholds in value. The transistor continues to turn n until the output is set at V as indicated by curve b.

If the capacitor had not been used the output could go I0 more negative than -V plus the two threshold voltages f transistor and 7. In other words, since the gate elecrode must always be more negative in value by at least )ne threshold than the source electrode, and since the volttge at the source of transistor 7 (and gate electrode 4) is ne threshold less than V, the voltage at the source f transistor 5 would be one threshold less than the volttge appearing at its gate electrode. Therefore, the output 'oltage would be two thresholds less negative than the upply voltage without capacitor C.

Inasmuch as the driver has inherent electrode capaciances and stray capacitances designated as C capacitor 3 must be selected so that the charge distribution on the :apacitors will provide the desired voltage increase at the :ate of transistor 5. C is also intended to include other tray capacitances of the device. The selection can be nade empirically or calculated mathematically if the other aircuit values are known.

For example, if C is much smaller than C, the effective apacitor will have little effect on the operation of the ircuit. However, if C is not small with respect to C, he charge will be distributed between the two capacitances .nd the effective voltage appearing at the gate may be educed. For example, if the capacitances are equal, the :harge would be equally distirbuted between capacitor C md effective capacitor C For the FIGURE 1 embodiment, the eflective gate voltage increase should be at least equivalent to two threshold voltages In other words, the ditference between the output and the gate should be equal to or greater than two threshold voltages in order. to completely turn transistor 12 on.

It should be pointed out that although transistor 7 is shown between the supply voltage and capacitor C it could be replaced by other devices [such as a relatively large resistor or diode, etc.,] that would hold the charge on the capacitor while the output is going negative.

Transistor 5 may be described as a switched resistor which has a high resistance when transistor 12 is on and a relatively lower resistance when transistor 12 is turned off. In other words, the resistance of the device decreases as the voltage at the gate increases. Because of the lower resistance, the transistor can be switched faster from off to on and can be used directly as an output driver without the addition of a push-pull stage as shown in FIGURE 2. The transistor can also be made smaller than normal, that is, a higher g transistor can be used without encountering normal voltage divider problems between transistor 5 and transistor 7. So long as the gate to source electrode voltage remains constant, the transistor functions as a constant current source.

Referring now to FIGURE 2, wherein is added pushpull stage 16, comprising transistors 17 and 18. Transistors 18 and 12 are turned on in the presence of a negative signal at the input. Transistor 17 is turned on when output 3 goes negative. Transistor 17 is made relatively large in size so that it can provide more current than could transistor 5. In other respects, the circuit is identical to the circuit shown in FIGURE 1.

Referring now to FIGURE 3, wherein is shown a second embodiment of a driver using capacitance feedback. The driver comprises MOS transistors 20 and 21 each having their respective gate electrodes connected to an input. Capacitor C is connected between drain electrode 22 of transistor 20 and drain electrode 23 of transistor 21. It is also connected between source electrode 24 of transistor 26 and source electrode 25 of transistor 27. The output is connected to source electrode 24 and drain electrode 22 of transistor 20 and 26. Delay capacitor C is connected between the output and ground. Effective capacitor C is represented by the dotted connection to ground.

Gate electrode 28 of transistor 26 is connected to one side of the capacitor C and also to the source electrode of transistor 27.

The gate electrode of transistor 27 is connected to supply voltage V so that the transistor is held on.

In operation, when the input is true, transistors 20 and 21 are turned on and both sides of the capacitor C are connected to ground. Transistor 20 and 21 are physically larger than transistor 27. When the input becomes false, transistors 20 and 21 are cut oil and the source electrode of transistor 27 goes negative by the amount of the supply voltage pluse the threshold voltage of the transistor.

Delay capacitor C prevents the output from going negative for a period of time sufiicient to permit capacitor C to charge to the value appearing at the source electrode of transistor 27. The output becomes negative after capacitor C is charged and as described in connection with FIGURE 1, the output is set at V.

Electrode capacitance C must be taken into account in selecting a value for capacitor C as was previously described for the FIGURE 1 embodiment.

Operation of the FIGURE 4 embodiment is approximately the same as the operation described in connection with the previous embodiments. The output of the device is delayed from going negative by means of delay capacitor C and delay transistor R Transistor R is used as a time constant resistor. R is held on because its gate electrode is connected to V. When the input is true, C charges to the true value of the input signal, which for the embodiment shown, is a negative voltage. When the input is false, C discharges to ground through R Transistor 30 remains on for a period of time sufiicient to permit capacitor C to charge to the value appearing at the source electrode of transistor 31. Subsequently, the output begins to go negative until it is equal to V.

Referring now to FIGURE 5, wherein is shown a representation of the FIGURE 1 embodiment produced on a silicon substrate, or chip. The other embodiments can be similarly produced. Although only one driver is shown, it should be obvious that several such devices could be produced simultaneously in a substrate. Also, a plurality of drivers and gating devices could be produced on the same substrate.

In the process, well known to those skilled in the art, an oxide film is formed over a substrate such as n type silicon. A p type substrate could also be used with the result that the devices formed would be 11 type instead of p type. Subsequently, holes are formed through the outside layers and impurities are dilfused into the silicon to form p type silicon. During the difiusion, an oxide layer forms over the diffused regions.

Following the dilfusion, the oxide layer where gate electrodes are to be formed, is thinned so that the gate voltage has greater effect on the conductance between electrodes of the MOS transistor formed.

After the thinning step is finished, holes are again formed through the outside layer and metal layers are disposed directly onto the diffused regions and over other areas of the substrate to form electrodes and contacts.

As shown in FIGURE 5, one dilfusion was required to form the p type regions for transistors 5, 7 and 12. The metal elements forming the input and gate 13 for transistor 12 are insulated from the 11 region and the p region (11 and 14) by a thin oxide layer (not apparent in the figure). When a negative signal appears on the input, the 11 type region separating electrodes 11 and 14, in effect, becomes p type silicon and conduction occurs between the electrodes. Since source electrode 14 is connected to the ground when the input is true, the output 3 has a near ground or zero volt level. The output electrode is also part of source electrode of transistor 5.

Drain electrode 15 is connected to supply voltage V. Transistor 7 comprising electrodes 9 and 6, was formed at the same time as the other transistor elements were formed. Gate electrode 8, shown connected to the supply voltage, is formed over the p type regions comprising electrodes 6 and 9 of transistor 7. Source electrode 6 is connected to gate electrode 4 of transistor 5.

Instead of separately forming capacitor C, and providing metal contacts to interconnect the capacitor with the driver, the capacitor may be formed as shown in FIGURE .5 by enlarging the metal element comprising gate electrode 4 to form one plate of the feedback capacitor. The other plate is comprised of p type material over which the capacitor plate is disposed.

The p type region comprising the other plate of the capacitor was enlarged in area to accommodate the metal plate. As a result of forming the capacitor in the manner described, one plate of the capacitor is integral with gate 4 and the other plate of the capacitor is integral with output 3 and drain electrode 11 of transistor 12.

Although a specific capacitor configuration is shown, it should be obvious that various capacitor sizes and configurations can be formed depending on the particular requirements of a circuit embodiment.

Although the invention has been described and illustrated in detail, it is to be understood that the same is by way of illustration and example only, and is not to be taken by way of limitation; the spirit and scope of this invention being limited only by the terms of the appended claims.

We claim:

[1. A MOS transistor driver having a voltage and current output, comprising,

capacitor means,

a voltage and current source,

first MOS transistor means having an output electrode a second electrode connected to said source, and a gate electrode,

said capacitor means being connected between said output electrode and said gate electrode for feeding back the output electrode voltage to the gate electrode after said capacitor is charged for turning said transistor on to set the output electrode to the voltage of said source,

first switch means connected between said source and gate electrode for inserting a relatively low resistance between said source and gate electrode while said capacitor is being charged, and for inserting a relatively high resistance between said source and said gate after said capacitor has been charged] [2. The combination as recited in claim 1, wherein said first switch means comprises a second MOS transistor means having a gate electrode and a first electrode connected to said source and a second electrode connected to the gate electrode of the first MOS transistor means] [3. The combination as recited in claim 1, including an input having a voltage level,

and second switch means including means responsive to said input for connecting said output electrode to a second voltage level while said capacitor is charging, and for disconnecting said output from said second voltage level after the capacitor has been charged] [4. The combination as recited in claim 3, wherein said first switch means comprises a second MOS transistor means having a gate electrode and a first electrode connected to said source and a second electrode connected to the gate electrode of said first MOS transistor means, and said second switch means comprises a third MOS transistor means having gate electrode connected to said input, a first electrode connected to said second voltagelevel, and a second electrode connected to said output] 5. A MOS transistor driver having a voltage and current output, comprising,

capacitor means,

a voltage source,

first MOS transistor means having an output electrode, a second electrode connected to said source, and a gate electrode,

said capacitor means being connected between said output electrode and said gate electrode for feeding back the output electrode voltage to the gate electrode after said capacitor is charged for turning said transistor on to set the output electrode to the voltage 07 said source,

first switch means connected between said source and gate electrode for inserting a relatively low resistance between said source and gate electrode while said capacitor is being charged, and for inserting a relatively high resistance between said source and said gate after said capacitor has been charged and further [5. The combination as recited in claim 1,] including an input having a voltage level,

and second switch means including means responsive to said input for connecting said output electrode to a second voltage level while said capacitor is charging, and for disconnecting said output from said second voltage level after the capacitor has been charged, including a delay capacitor connected between said output electrode and said second voltage level for delaying disconnecting the output electrode from said second voltage level until said delay capacitor has been charged, said delay being suflicient to enable said capacitor means to charge to said first voltage level[s], and third switch means responsive to the input for connecting said gate electrode to said second voltage level while said output is connected to said second level, and for disconnecting said gate from said second voltage level prior to the charging of said delay capacitor.

6. A MOS transistor driver having a voltage and curent output, comprising,

first electrode and the output towards said first voltage level,

said voltage diflerence on said control electrode being increased by voltage fed back through said capacitor from said first electrode for enhancing the first field effect transistor until the voltage on said first electrode and the output is equal to said first voltage leveL] [10. The combination recited in claim 1 further including a delay capacitor connected between said second electrode and said second voltage level, said delay capacitor being charged to the difference between said first and second voltage levels during the period said first field efiect transistor is operable,

gate electrode for inserting a relatively low resistance a third wit h mean for connecting the control elecbslwee" said source and 81118 6196" ads While said trode of said first field eflect transistor to said second Capacitor is being g and f inserting a relavoltage level during a first phase of an input signal, high resistance between said source and said said third switch means disconnecting said control gate after said Capacitor has been charg d a f electrode from said second voltage level during a The Combination as recited in Claim second phase of the input signal for enabling said Cluding an input having 3 Voltage level, and seCOlld first recited capacitor to charge to said voltage difswitch means including means responsive to said f input for Connecting said Output electrode to a second said second switch means comprising, a field effect tran- Voltage lsvfil While said Capacitor is charging, and sister for connecting said second electrode to said disconnecting said Output from said second Volt" second voltage level during the first phase of the inage level after the capacitor has been charged, including a delay capacitor connected between the input and the second voltage level to the second switch means, and a delay resistor means connected between said input and the delay capacitor for delaying said second switch means for disconnecting the output from said second voltage level while said delay capacitor is charging to the voltage level of said input through said delay resistor.

7. The combination as recited in claim 6, wherein said lelay resistor means comprises a MOS transistor having a gate electrode connected to said source, a first electrode said second switch mean-s comprising, a third field effect transistor connected between said :onnected to said input, and a second electrode connected 0 the capacitor and the second switch means.

first electrode and said second voltage level and having a control electrode,

[8. In combination, a delay capacitor connected between said control elecfirst MOS transistor means having a first electrode, an trOdc and Said second Voltage level,

output electrode and a gate electrod a delay field effect transistor having a control electrode source means connected to said first electrode for supconnected to said fiIst Voltage level and a first e166- plying voltage and urrent to id output el t d trode connected to the control electrode of said third when said transistor i turn d on, field efiect transistor and to said delay capacitor, and capacitor means, said delay field elfect transistor further having a secmeans connected to both sides of said capacitor means 0nd electrode receiving said input signal,

for charging said capacitor to a voltage level during said delay field effect transistor being opfilable during a first interval of time, including switch means for a first Phase of said input signal for Tndering said preventing discharge of said capacitor after it is 5 third field eifect transistor becoming operable, said charged, said capacitor being connected between the delay Capacitor charging t0 the difference bet-"Ween output said said gate, said capacitor voltage charge said input signal and Said seCOnd Voltage level during plus the output voltage turning the first transistor on said first P for setting the output to the vlotage of said source said delay field efiest transistor Providing a dissharge means] pattern for said delay capacitor during said second [9. A field effect transistor amplifier having an output p said third fi effect transistor being held n ,nd comprising, an operable condition for a period of time detera first field effect transistor having a first electrode conmined y the time constant of said fi efiect nected to said output, second electrode connected to and said delay capacitor, said Period of a first voltage level and a control electrode, 0 time being sufficient to enable said first recited capaca capacitor connected between said first electrode and said control electrode,

a first switch means connected between said first voltage level and said control electrode for charging said itor to charge to the difference voltage] 12. A field efiect transistor amplifier having an output and comprising a first field effect transistor having a first electrode concapacitor and for providing a relatively high imnected to said output, second electrode connected pedance between said first voltage level and said conto a first voltage level and a control electrode,

trol electrode after said capacitor is charged. a capacitor connected between said first electrode and a second switch means for connecting said first elccsaid control electrode,

trode to a second voltage level for charging said caa first switch means connected between said first voltage pacitor to the voltage difierence between said first level and said control electrode for charging said and second voltage levels and for disconnecting said first electrode from said second voltage level after said capacitor is charged.

said first field eliect transistor being responsive to the voltage difference on said capacitor for driving said capacitor and for providing a relatively high impedance between said first voltage level and said control electrode after said capacitor is charged,

a second switch means for connecting said first electrode to a second voltage level during a first phase of an input signal for enabling said capacitor to be charged to the difierence between said first voltage level and said second voltage level and for disconnecting said first electrode from said second voltage level after said capacitor is charged,

said first field effect transistor being responsive to the voltage difierence on said capacitor for driving said first electrode and the output towards said first voltage level,

said voltage difierence on said control electrode being increased by voltage fed back through said capacitor from said first electrode for enhancing the conduction of the first field eflect transistor until the voltage on said first electrode and the output is equal to said first voltage level,

a delay capacitor connected between said first electrode and said second voltage level, said delay capacitor being charged to the difierence between said first and second voltage levels during the period said first field efiect transistor is operable,

a third switch means for connecting the control electrode of said first field efiect transistor to said second voltage level during a first phase of an input signal, said third switch means disconnecting said control electrode from said second voltage level during a second phase of the input signal for enabling said first recited capacitor to charge to said voltage difierence.

said delay capacitor having a charge time for delaying disconnecting said first electrode from said second voltage level until the first recited capacitor is charged to the voltage difierence.

13. A field eflec't transistor amplifier having an output and comprising,

a first field efiect transistor having a first electrode connected to said output, second electrode connected to first voltage level and a control electrode,

a capacitor connected between said first electrode and said control electrode,

a first switch means connected between said first voltage level and said control electrode for charging said capacitor and for providing a relatively high impedance between said first voltage level and said control electrode for charging said capacitor and for providing a relatively high impedance between said first voltage level and said control electrode after said capacitor is charged,

a second switch means for connecting said first electrode to a second voltage level for charging said capacitor to the voltage difference between said first and second voltage levels and for disconnecting said first electrode from said second voltage level after asid capacitor is charged,

said first field effect transistor being responsive to the voltage difierence on said capacitor for driving said first electrode and the output towards said first voltage level.

said voltage difference on said control electrode being increased by voltage fed back through said capacitor from said first electrode for enhancing the conduction of the first field effect transistor until the voltage on said first electrode and the output is equal to said first voltage level,

a second field efiect transistor for connecting the control electrode of the first field effect transistor to said second voltage level during a first phase of an imput signal,

said second switch means comprising a third field efiect transistor connected between said first electrode and said second voltage level and having a control electrode,

a delay capacitor connected between said con trol electrode and said second voltage level.

a delay field efiect transistor having a control electrode connected to said first voltage level and a first electrode connected to the control electrode of said third field efiect transistor and to said delay capacitor, and said delay field efiect transistor further having a second electrode for receiving said input signal,

said delay field efiect transistor being operable during a first phase of said input signal for rendering said third field efiect transistor operable, said delay capacitor charging to the defieren'ce between said input signal and said second voltage level during said first phase,

said delay field efiect transistor providing a discharge path for said delay capacitor during said second phase, said third field efiect transistor being held in an operable condition for a period of time determined by the RC time constant of said delay field efiect transistor and said delay capacitor, said period of time being sufficient to enable said first recited capacitor to charge to the difierence voltage.

12/1962 Evans.

11/1966 Michell et al. 307251 FOREIGN PATENTS 28,884 12/1968 Japan.

STANLEY D. MILLER, 1a., Primary Examiner B. P. DAVIS, Assistant Examiner US. Cl. X.R. 

